Processing technologies and device structures for forming integrated circuits (ICs) are often implemented by using a plurality of interconnected field effect transistors (FETs), also called metal-oxide-semiconductor field effect transistors (MOSFETs), or simply MOS transistors or devices. Although the term “MOS” properly refers to a device having a metal gate electrode and an oxide gate insulator, that term will be used throughout to refer to any semiconductor device that includes a conductive gate electrode (whether metal or not) that is positioned over a gate insulator (whether oxide or other dielectric material) which, in turn, is positioned over a semiconductor surface. Accordingly, the terms metal-oxide-semiconductor and the abbreviations “MOS” and “MOSFET” are used herein even though such devices may not employ just metals or oxides but combinations of conductive materials, e.g., alloys, silicides, doped semiconductors, etc., instead of simple metals, and insulating materials other than silicon oxides (e.g., nitrides, oxy-nitrides, other oxides mixtures of dielectric materials, etc.). Thus, as used hereon the terms MOS and MOSFET are intended to include such variations.
A typical MOS transistor includes a gate as a control electrode and spaced-apart source and drain regions between which a current can flow. A control voltage applied to the gate adjusts the flow of current through a controllable conductive channel between the source and drain. It is well known in the art that a pair of two identical MOSFETs can form a simple current mirror with 1:1 ratio. A current mirror is a device in which a reference current (I-ref.) flowing through one MOSFET is replicated in the parallel MOSFET. The replicated current, also called the mirror current (I-mir.), is then used to supply a precisely determined current to other parts of the circuit without impact on the reference current itself. Similarly, it is well known in the art to series connect two MOSFETs to form a “Cascode” amplifier. A pair of such cascode amplifiers can be connected to form a cascode current mirror. Compared to a simple two transistor current mirror, a cascode mirror can reduce the error that can arise due to the finite output impedance of the MOSFETs and provide more precise mirror current. Cascode current mirrors are widely used in high precision analog circuits. For convenience of description and not intended to be limiting, n-channel (NMOS) cascode mirrors are illustrated herein, but persons of skill in the art will understand that the present invention is not limited merely to n-channel mirrors and that p-channel (PMOS) and other types of devices may be provided by substitution of semiconductor regions of opposite conductivity type.
FIG. 1 shows a simplified schematic circuit diagram of current mirror cascode 20. Reference current (left) side cascode 22 comprises lower or bottom transistor T1 series coupled to upper or top transistor T2. For an NMOS cascode, reference current I-ref. flows from terminal 23 through T2 and T1 to terminal 24 while for a PMOS cascode, the current direction is opposite. Gate 25 of transistor T1 is coupled to node 27 which is in turn coupled to node 21 located between T1 and T2. Gate 26 of transistor T2 is coupled to node 28 which is in turn coupled to node 29 between transistor T2 and terminal 23. In other words, for each transistor (T1 or T2), its gate (25 or 26) is tied to its drain (21 or 29), respectively.
Mirror current (right) side cascode 32 comprises lower or bottom transistor T3 series coupled to upper or top transistor T4. For an NMOS cascode, mirror current I-mir flows from terminal 33 through T4 and T3 to terminal 34. Gate 35 of transistor T3 is coupled to node 27 which is in turn coupled to node 21 located between T1 and T2. Gate 36 of transistor T2 is coupled to node 28 which is in turn coupled to node 29 between transistor T2 and terminal 23. Gates 25 and 35 are coupled together and gates 26 and 36 are coupled together. It is common in the art to refer to Transistors T2, T4 as the “upper transistors” or “top” of cascode mirror 20 and transistors T1, T3 as the “lower transistors” or “bottom” of cascode mirror 20. The words “upper” and “top” are used interchangeably herein as are the words “lower” and “bottom”. Vg1 refers to the gate voltage on gates 25, 35 (collectively first gates G1) of bottom transistors T1, T3 and Vg2 refers to the voltage on gates 26, 36 (collectively second gates G2) of top transistors T2, T4. Nodes 24 and 34 are generally connected to the same reference voltage (for NMOS, for example, Vref=0). Both Vg1 and Vg2 are determined by reference current I-ref. Often, the voltage bias on node 33 is different from that on node 23 (or Vg2) and use of the cascode structure can correct the error induced by such bias difference.
FIG. 2 shows a simplified schematic cross-sectional view through NMOS cascode amplifier 40 suitable for use in a cascode current mirror, according to the prior art. FIG. 3 shows a simplified schematic plan view of two prior art cascode amplifiers of the type illustrated in FIG. 2, arranged to form cascode current mirror 72 implementing circuit 20 of FIG. 1. Other than the interconnections used to form the current mirror, the cascode amplifiers in FIG. 3 are assumed to be substantially identical. The same reference numbers are used in FIGS. 2 and 3 to identify like regions, with primes (′) added to indicate those regions of the second cascode amplifier needed to form the current mirror. For convenience of explanation, various construction details have been omitted in FIGS. 2 and 3. For example, the interconnection layers needed to interconnect various regions of amplifiers 40, 40′ in FIG. 3 have been omitted to avoid obscuring underlying device regions, and these interconnections are shown schematically. For convenience of explanation, the prior art and the invention are described for the case of N-channel devices, but this is not intended to be limiting and persons of skill in the art will understand based on the description herein that P-channel devices can be constructed by replacing N-type regions with P-type regions and vice versa. Single cascode amplifier 40 is illustrated in FIG. 2 and two cascode amplifiers 40, 40′ of the type shown in FIG. 2 are illustrated in FIG. 3, interconnected to form cascode current mirror 72 implementing circuit 20 of FIG. 1. FIGS. 2 and 3 should be considered together. To facilitate relating the transistors (T1, T2, T3, T4) of FIG. 1 to those of FIGS. 2-3, the same identifying labels (e.g., T1, T2, T3, T4) are used but with the suffix “old” added to specifically denote the transistors of FIGS. 2-3, that is, T1old, T2old, T3old, T4old. The same convention is followed for other identifying labels, e.g., G1old, G2old.
Cascode amplifier 40 comprises P-type substrate or region 41 (often a doped “well”), N+ region 42 that acts as a source (S) region for lower transistor T1old, N+ region 43 that serves simultaneously as a drain (D) region for lower transistor T1old and a source (S) region for upper transistor T2old (collectively D/S region 43), and N+ region 44 that serves as the drain (D) region for upper transistor T2old. First gate (G1old) 45 overlies gate dielectric 47 of thickness 471 above channel region 49 between source (S) region 42 and D/S region 43, and second gate (G2old) overlies gate dielectric 48 of thickness 481 above channel region 50 between D/S region 43 and drain (D) region 44. When cascode amplifier 40 is appropriately biased, source-drain electron current Isdold (in an N-channel device) flows through channels 49, 50. In FIG. 3 implementing current mirror 20, cascode amplifier 40 is assumed to form reference side 401 and substantially identical cascode amplifier 40′ is assumed to form mirror side 402. When arranged as in circuit 20 of FIG. 1, source 42 of transistor T1old of cascode amplifier 40 is coupled to terminal 24 and drain 44 of transistor T2old is coupled to terminal 23. Similarly, source 42′ of transistor T3old of cascode amplifier 40′ is coupled to terminal 34 and drain 44′ of transistor T4old is coupled to terminal 33. Gates 45 and 45′ of transistors T1old, T3old are coupled together at node 27 and to D/S region 43 of reference side cascode amplifier 40 at node 21. Similarly, gates 46 and 46′ of transistors T2old, T4old are coupled together at node 28 and to drain region 44 of reference side cascode amplifier 40 at node 29. In conventional cascode current mirror 72, gates 45, 45′ and 46, 46′ of transistors T1old, T3old and T2old, T4old have substantially equal gate areas and substantially equal gate dielectric thicknesses 471, 481, 471′, 481′, where the unprimed and primed (′) reference numbers refer to the various elements of cascode amplifiers 40, 40′ used for reference current side 401 and mirror current side 402 of current mirror 72, respectively. Further, the ratios R=L/W of channel length L to channel width W of the top and bottom devices in the prior art are generally substantially the same.
There is a great need in forming advanced precision analog integrated circuits to shrink the chip area occupied by such cascode current mirrors to smaller and smaller dimensions. However, as the devices making up the cascode mirror are reduced in size, the matching between the devices that make up reference and current mirror sides 401, 402 deteriorates and the noise performance worsens. This arises because the inevitable manufacturing variations become a larger fraction of the device dimensions as the device dimensions are shrunk and, therefore, have a proportionately greater affect on the device properties, especially device matching. A further problem is that there is an ongoing trend to reduce supply voltages. This means that the voltage available to provide gate overdrive voltage is also decreasing. The gate overdrive voltage (Vod) is the amount by which the available gate drive voltage (Vg) exceeds the device threshold voltage (Vth), that is, Vod=Vg−Vth. For the same threshold voltage Vth, if the available supply voltage Vsupp is reduced, the available overdrive voltage Vod is also reduced and the worse the mismatch and noise problems become. Thus, as supply voltages are reduced, mismatch and noise problems become more severe. While the increased mismatch and noise associated with lower operating voltages can be avoided or mitigated by increasing the gate area, this is not an economically viable solution for advanced smaller area circuits.
Accordingly, there is an ongoing need and desire to provide improved cascode current mirror devices and methods adapted to operate at lower supply voltages without increasing the mismatch. In addition, it is desirable to provide a structure and method for fabricating cascode current mirrors that are shrinkable to smaller dimensions without sacrificing performance or increasing mismatch. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.